A FPGA IMPLEMENTATION OF A PHASE LOCKED LOOP FOR DC MOTOR CONTROL BY BOGDAN ALECSA and ALEXANDRU ONEA

The paper proposes a way of implementing a phase locked loop (PLL) motor speed controller. The main emphasis is on the FPGA implementation of the digital PLL. The closed loop sensing element is an optical tachometer, which outputs an impulse train with a frequency proportional to the motor rotational speed. This impulse train will be synchronized by the PLL to a reference impulse train of a given precise frequency, generated inside the FPGA from a quartz crystal oscillator. The phase difference between the two impulse trains is measured by a phase detector. The phase detector converts the phase difference to a numerical value that can be processed digitally by the loop filter. The loop filter acts as a regulator. The novelty of the design is the phase detector, which allows digital processing of the signals. The design of the PLL can be done only with digital logic. The whole digital controller can be easily implemented in an FPGA. Simulation results show the behaviour of the designed digital circuits.